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19-2719; Rev 0; 04/03
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
General Description
The MAX1261/MAX1263 low-power, 12-bit analog-todigital converters (ADCs) feature a successive-approximation ADC, automatic power-down, fast wake-up (2s), an on-chip clock, +2.5V internal reference, and a high-speed, byte-wide parallel interface. They operate with a single +3V analog supply and feature a VLOGIC pin that allows them to interface directly with a +1.8V to +5.5V digital supply. Power consumption is only 5.7mW (VDD = VLOGIC) at the maximum sampling rate of 250ksps. Two softwareselectable power-down modes enable the MAX1261/ MAX1263 to be shut down between conversions; accessing the parallel interface returns them to normal operation. Powering down between conversions can cut supply current to under 10A at reduced sampling rates. Both devices offer software-configurable analog inputs for unipolar/bipolar and single-ended/pseudo-differential operation. In single-ended mode, the MAX1261 has eight input channels and the MAX1263 has four input channels (four and two input channels, respectively, when in pseudo-differential mode). Excellent dynamic performance and low power, combined with ease of use and small package size, make these converters ideal for battery-powered and dataacquisition applications or for other circuits with demanding power consumption and space requirements. The MAX1261 is available in a 28-pin QSOP package, while the MAX1263 is available in a 24-pin QSOP. For pin-compatible +5V, 12-bit versions, refer to the MAX1262/MAX1264 data sheet. o 12-Bit Resolution, 0.5 LSB Linearity o +3V Single Operation o User-Adjustable Logic Level (+1.8V to +3.6V) o Internal +2.5V Reference o Software-Configurable, Analog Input Multiplexer 8-Channel Single Ended/ 4-Channel Pseudo-Differential (MAX1261) 4-Channel Single Ended/ 2-Channel Pseudo-Differential (MAX1263) o Software-Configurable, Unipolar/Bipolar Inputs o Low Power 1.9mA (250ksps) 1.0mA (100ksps) 400A (10ksps) 2A (Shutdown) o Internal 3MHz Full-Power Bandwidth Track/Hold o Byte-Wide Parallel (8 + 4) Interface o Small Footprint 28-Pin QSOP (MAX1261) 24-Pin QSOP (MAX1263)
Features
MAX1261/MAX1263
Pin Configurations
TOP VIEW
HBEN 1 D7 2 D6 3 D5 4 28 VLOGIC 27 VDD 26 REF 25 REFADJ 24 GND
Applications
Industrial Control Systems Energy Management Data-Acquisition Systems Data Logging Patient Monitoring Touch Screens
D4 5 D3/D11 6 D2/D10 7 D1/D9 8 D0/D8 9
MAX1261
23 COM 22 CH0 21 CH1 20 CH2 19 CH3 18 CH4 17 CH5 16 CH6 15 CH7
Ordering Information
PART MAX1261ACEI MAX1261BCEI MAX1261AEEI MAX1261BEEI TEMP RANGE 0C to +70C 0C to +70C -40C to +85C -40C to +85C PIN-PACKAGE 28 QSOP 28 QSOP 28 QSOP 28 QSOP INL (LSB) 0.5 1 0.5 1
INT 10 RD 11 WR 12 CLK 13 CS 14
QSOP
Pin Configurations continued at end of data sheet. Typical Operating Circuits appear at end of data sheet. 1
Ordering Information continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V VLOGIC to GND.........................................................-0.3V to +6V CH0-CH7, COM to GND ............................-0.3V to (VDD + 0.3V) REF, REFADJ to GND ................................-0.3V to (VDD + 0.3V) Digital Inputs to GND ...............................................-0.3V to +6V Digital Outputs (D0-D11, INT) to GND...-0.3V to (VLOGIC + 0.3V) Continuous Power Dissipation (TA = +70C) 24-Pin QSOP (derate 9.5mW/C above +70C) ..........762mW 28-Pin QSOP (derate 8.0mW/C above +70C) ..........667mW Operating Temperature Ranges MAX1261_C_ _/MAX1263_C_ _ ..........................0C to +70C MAX1261_E_ _/MAX1263_E_ _ .......................-40C to +85C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER DC ACCURACY (Note 1) Resolution Relative Accuracy (Note 2) Differential Nonlinearity Offset Error Gain Error Gain Temperature Coefficient Channel-to-Channel Offset Matching Signal-to-Noise Plus Distortion Total Harmonic Distortion (Including 5th-Order Harmonic) Spurious-Free Dynamic Range Intermodulation Distortion Channel-to-Channel Crosstalk Full-Linear Bandwidth Full-Power Bandwidth CONVERSION RATE External clock mode Conversion Time (Note 5) Track/Hold Acquisition Time Aperture Delay Aperture Jitter External Clock Frequency Duty Cycle 2 fCLK tCONV tACQ External acquisition or external clock mode External acquisition or external clock mode Internal acquisition/internal clock mode 0.1 30 50 <50 <200 4.8 70 External acquisition/internal clock mode Internal acquisition/internal clock mode 3.3 2.5 3.2 3.0 3.6 3.5 4.1 625 ns ns ps MHz % s SINAD THD SFDR IMD fIN1 = 49kHz, fIN2 = 52kHz fIN = 125kHz, VIN = 2.5VP-P (Note 4) SINAD > 68dB -3dB rolloff 80 76 -78 250 3 67 (Note 3) 2.0 0.2 RES INL DNL MAX126_A MAX126_B No missing codes overtemperature 12 0.5 1 1 4 4 Bits LSB LSB LSB LSB ppm/C LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC SPECIFICATIONS (fIN(sine wave) = 50kHz, VIN = 2.5VP-P, 250ksps, external fCLK = 4.8MHz, bipolar input mode) 70 -78 dB dB dB dB dB kHz MHz
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ANALOG INPUTS Analog Input Voltage Range, Single Ended and Differential (Note 6) Multiplexer Leakage Current Input Capacitance INTERNAL REFERENCE REF Output Voltage REF Short-Circuit Current REF Temperature Coefficient REFADJ Input Range REFADJ High Threshold Load Regulation Capacitive Bypass at REFADJ Capacitive Bypass at REF EXTERNAL REFERENCE AT REF REF Input Voltage Range REF Input Current DIGITAL INPUTS AND OUTPUTS Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance Output Low Voltage Output High Voltage Tri-State Leakage Current Tri-State Output Capacitance VIH VIL VHYS IIN CIN VOL VOH ILEAKAGE COUT ISINK = 1.6mA ISOURCE = 1mA CS = VDD CS = VDD VLOGIC - 0.5 0.1 15 1 VIN = 0 or VDD VLOGIC = 2.7V VLOGIC = 1.8V VLOGIC = 2.7V VLOGIC = 1.8V 200 0.1 15 0.4 1 2.0 1.5 0.8 0.5 V V mV A pF V V A pF VREF IREF VREF = 2.5V, fSAMPLE = 250ksps Shutdown mode 1.0 200 VDD + 50mV 300 2 V A 4.7 TCREF TA = 0C to +70C For small adjustments To power down the internal reference 0 to 0.5mA output load (Note 7) VDD - 1.0 0.2 0.01 1 10 2.49 2.5 15 20 100 2.51 V mA ppm/C mV V mV/mA F F CIN VIN Unipolar, VCOM = 0 Bipolar, VCOM = VREF / 2 On-/off-leakage current, VIN = 0 or VDD 0 -VREF/2 0.01 12 VREF +VREF/2 1 A pF V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1261/MAX1263
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX unless otherwise noted. Typical values are at TA = +25C.) PARAMETER POWER REQUIREMENTS Analog Supply Voltage Digital Supply Voltage VDD VLOGIC Operating mode, fSAMPLE = 250ksps Positive Supply Current IDD Standby mode Shutdown mode VLOGIC Current Power-Supply Rejection ILOGIC PSR CL = 20pF fSAMPLE = 250ksps Not converting 2 0.4 Internal reference External reference Internal reference External reference 2.7 1.8 2.3 1.9 0.9 0.5 2 3.6 VDD + 0.3 2.6 2.3 1.2 0.8 10 150 10 0.9 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
mA A A mV
VDD = 3V 10%, full-scale input
TIMING CHARACTERISTICS
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CLK Period CLK Pulse Width High CLK Pulse Width Low Data Valid to WR Rise Time WR Rise to Data Valid Hold Time WR to CLK Fall Setup Time CLK Fall to WR Hold Time CS to CLK or WR Setup Time CLK or WR to CS Hold Time CS Pulse Width WR Pulse Width CS Rise to Output Disable SYMBOL tCP tCH tCL tDS tDH tCWS tCWH tCSWS tCSWH tCS tWR tTC (Note 8) CLOAD = 20pF (Figure 1) CONDITIONS MIN 208 40 40 40 0 40 40 60 0 100 60 20 100 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns
4
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
TIMING CHARACTERISTICS (continued)
(VDD = VLOGIC = +2.7V to +3.6V, COM = GND, REFADJ = VDD, VREF = +2.5V, 4.7F capacitor at REF pin, fCLK = 4.8MHz (50% duty cycle); TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER RD Rise to Output Disable RD Fall to Output Data Valid HBEN to Output Data Valid RD Fall to INT High Delay CS Fall to Output Data Valid SYMBOL tTR tDO tDO1 tINT1 tDO2 CONDITIONS CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 CLOAD = 20pF, Figure 1 MIN 20 20 20 TYP MAX 70 70 110 100 110 UNITS ns ns ns ns ns
MAX1261/MAX1263
Note 1: Tested at VDD = +3V, COM = GND, unipolar single-ended input mode. Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after offset and gain errors have been removed. Note 3: Offset nulled. Note 4: On channel is grounded; sine wave applied to off channels. Note 5: Conversion time is defined as the number of clock cycles times the clock period; clock has 50% duty cycle. Note 6: Input voltage range referenced to negative input. The absolute range for the analog inputs is from GND to VDD. Note 7: External load should not change during conversion for specified accuracy. Note 8: When bit 5 is set low for internal acquisition, WR must not return low until after the first falling clock edge of the conversion.
VLOGIC 3k DOUT 3k CLOAD 20pF DOUT CLOAD 20pF
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
Figure 1. Load Circuits for Enable/Disable Times
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Typical Operating Characteristics
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SAMPLE FREQUENCY
MAX1261/63 toc02 MAX1261/63 toc03
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.4 0.3 0.2 DNL (LSB) INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1000 2000 3000 4000 5000 DIGITAL OUTPUT CODE
MAX1261/63 toc01
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1000 2000 3000 4000 5000 DIGITAL OUTPUT CODE 1 0.1 1 10 10,000
0.5
1000 IDD (A)
WITH INTERNAL REFERENCE
100 WITH EXTERNAL REFERENCE
10
100
1k
10k
100k
1M
fSAMPLE (Hz)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc04
SUPPLY CURRENT vs. TEMPERATURE
MAX1261/63 toc05
STANDBY CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc06
2.10 2.05 2.00 IDD (mA) 1.95 1.90 1.85 1.80 2.7 3.0
RL = CODE = 101010100000
2.2 2.1 2.0 IDD (mA) 1.9 1.8 1.7 1.6
RL = CODE = 101010100000
930
920 STANDBY IDD (A)
910
900
890
880 -40 -15 10 35 60 85 2.7 3.0 VDD (V) 3.3 3.6 TEMPERATURE (C)
3.3 VDD (V)
3.6
STANDBY CURRENT vs. TEMPERATURE
MAX1261/63 toc07
POWER-DOWN CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc08
POWER-DOWN CURRENT vs. TEMPERATURE
MAX1261/63 toc09
930
1.50
1.2
920 STANDBY IDD (A)
POWER-DOWN IDD (A)
910
1.00
POWER-DOWN IDD (A)
1.25
1.1
1.0
900
890
0.75
0.9
880 -40 -15 10 35 60 85 TEMPERATURE (C)
0.50 2.7 3.0 VDD (V) 3.3 3.6
0.8 -40 -15 10 35 60 85 TEMPERATURE (C)
6
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Typical Operating Characteristics (continued)
(VDD = VLOGIC = +3V, VREF = +2.500V, fCLK = 4.8MHz, CL = 20pF, TA = +25C, unless otherwise noted.)
MAX1261/MAX1263
INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE
MAX1261/63 toc10
INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE
MAX1261/63 toc11
OFFSET ERROR vs. SUPPLY VOLTAGE
MAX1261/63 toc12
2.53
2.53
0.0
2.52
2.52
-0.5 OFFSET ERROR (LSB)
VREF (V)
2.50
VREF (V)
2.51
2.51
-1.0
2.50
-1.5
2.49
2.49
-2.0
2.48 2.7 3.0 VDD (V) 3.3 3.6
2.48 -40 -15 10 35 60 85 TEMPERATURE (C)
-2.5 2.7 3.0 VDD (V) 3.3 3.6
OFFSET ERROR vs. TEMPERATURE
MAX1261/63 toc13
GAIN ERROR vs. SUPPLY VOLTAGE
MAX1261/63 toc14
GAIN ERROR vs. TEMPERATURE
MAX1261/63 toc15
0.5 0.0 OFFSET ERROR (LSB) -0.5 -1.0 -1.5 -2.0 -2.5 -40 -15 10 35 60
1
0.5
0.0 GAIN ERROR (LSB)
0 GAIN ERROR (LSB)
-0.5
-1
-1.0
-2
-1.5
-3 85 2.7 3.0 VDD (V) 3.3 3.6 TEMPERATURE (C)
-2.0 -40 -15 10 35 60 85 TEMPERATURE (C)
LOGIC SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX1261/63 toc16
LOGIC SUPPLY CURRENT vs. TEMPERATURE
MAX1261/63 toc17
FFT PLOT
0 -20 AMPLITUDE (dB) -40 -60 -80 -100 -120 VDD = 3V fIN = 50kHz fSAMPLE = 250ksps
MAX1261/63 toc18
250
250
20
200 ILOGIC (A)
200 ILOGIC (A)
150
150
100
100
50 2.7 3.0 VDD (V) 3.3 3.6
50 -40 -15 10 35 60 85 TEMPERATURE (C)
-140 0 200 400 600 800 1000 1200 FREQUENCY (kHz)
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Pin Description
PIN MAX1261 1 2 3 4 5 6 7 8 9 10 11 MAX1263 1 2 3 4 5 6 7 8 9 10 11 NAME FUNCTION High Byte Enable. Used to multiplex the 12-bit conversion result: 1: Four MSBs are multiplexed on the data bus. 0: Eight LSBs are available on the data bus. Tri-State Digital I/O Line (D7) Tri-State Digital I/O Line (D6) Tri-State Digital I/O Line (D5) Tri-State Digital I/O Line (D4) Tri-State Digital I/O Line (D3, HBEN = 0; D11, HBEN = 1) Tri-State Digital I/O Line (D2, HBEN = 0; D10, HBEN = 1) Tri-State Digital I/O Line (D1, HBEN = 0; D9, HBEN = 1) Tri-State Digital I/O Line (D0, HBEN = 0; D8, HBEN = 1) INT goes low when the conversion is complete and the output data is ready. Active-Low Read Select. If CS is low, a falling edge on RD enables the read operation on the data bus. Active-Low Write Select. When CS is low in internal acquisition mode, a rising edge on WR latches in configuration data and starts an acquisition plus a conversion cycle. When CS is low in external acquisition mode, the first rising edge on WR ends acquisition and starts a conversion. Clock Input. In external clock mode, drive CLK with a TTL-/CMOS-compatible clock. In internal clock mode, connect this pin to either VDD or GND. Active-Low Chip Select. When CS is high, digital outputs (D7-D0) are high impedance. Analog Input Channel 7 Analog Input Channel 6 Analog Input Channel 5 Analog Input Channel 4 Analog Input Channel 3 Analog Input Channel 2 Analog Input Channel 1 Analog Input Channel 0 Ground Reference for Analog Inputs. Sets zero-code voltage in single-ended mode and must be stable to 0.5 LSB during conversion. Analog and Digital Ground Bandgap Reference Output/Bandgap Reference Buffer Input. Bypass to GND with a 0.01F capacitor. When using an external reference, connect REFADJ to VDD to disable the internal bandgap reference. Bandgap Reference Buffer Output/External Reference Input. Add a 4.7F capacitor to GND when using the internal reference. Analog +5V Power Supply. Bypass with a 0.1F capacitor to GND. Digital Power Supply. VLOGIC powers the digital outputs of the data converter and can range from +1.8V to (VDD + 300mV).
HBEN D7 D6 D5 D4 D3/D11 D2/D10 D1/D9 D0/D8 INT RD
12
12
WR
13 14 15 16 17 18 19 20 21 22 23 24 25
13 14 -- -- -- -- 15 16 17 18 19 20 21
CLK CS CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 COM GND REFADJ
26 27 28
22 23 24
REF VDD VLOGIC
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Detailed Description
Converter Operation
The MAX1261/MAX1263 ADCs use a successiveapproximation (SAR) conversion technique and an input track/hold (T/H) stage to convert an analog input signal to a 12-bit digital output. Their parallel (8 + 4) output format provides an easy interface to standard microprocessors (Ps). Figure 2 shows the simplified internal architecture of the MAX1261/MAX1263. either of the analog inputs. This configuration is pseudodifferential in that only the signal at IN+ is sampled. The return side (IN-) must remain stable within 0.5 LSB (0.1 LSB for best performance) with respect to GND during a conversion. To accomplish this, connect a 0.1F capacitor from IN- (the selected input) to GND. During the acquisition interval, the channel selected as the positive input (IN+) charges capacitor CHOLD. At the end of the acquisition interval, the T/H switch opens, retaining charge on CHOLD as a sample of the signal at IN+. The conversion interval begins with the input multiplexer switching CHOLD from the positive input (IN+) to the negative input (IN-). This unbalances node zero at the comparator's positive input. The capacitive digital-toanalog converter (DAC) adjusts during the remainder of the conversion cycle to restore node 0 to 0V within the limits of 12-bit resolution. This action is equivalent to transferring a 12pF[(VIN+) - (VIN-)] charge from CHOLD to the binary-weighted capacitive DAC, which in turn forms a digital representation of the analog input signal.
MAX1261/MAX1263
Single-Ended and Pseudo-Differential Operation
The sampling architecture of the ADC's analog comparator is illustrated in the equivalent input circuit in Figure 3. In single-ended mode, IN+ is internally switched to channels CH0-CH7 for the MAX1261 (Figure 3a) and to CH0-CH3 for the MAX1263 (Figure 3b), while IN- is switched to COM (Table 3). In differential mode, IN+ and IN- are selected from analog input pairs (Table 4) and are internally switched to
REF
REFADJ 17k
(CH7) (CH6) (CH5) (CH4) CH3 CH2 CH1 CH0 COM
AV = 2.05
1.22V REFERENCE
ANALOG INPUT MULTIPLEXER
T/H CHARGE REDISTRIBUTION 12-BIT DAC 12 SUCCESSIVEAPPROXIMATION REGISTER COMP
CLK
CLOCK 4 8 8 MUX
CS WR RD INT 8 CONTROL LOGIC AND LATCHES
4
MAX1261 MAX1263
HBEN VDD VLOGIC GND
8 TRI-STATE, BIDIRECTIONAL I/O INTERFACE D0-D7 8-BIT DATA BUS
( ) ARE FOR MAX1261 ONLY.
Figure 2. Simplified Internal Architecture for 8-/4-Channel MAX1261/MAX1263 _______________________________________________________________________________________ 9
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Track/Hold
12-BIT CAPACITIVE DAC REF INPUT CHOLD MUX - + 12pF CSWITCH TRACK T/H SWITCH RIN 800 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. COMPARATOR ZERO
CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM
SINGLE-ENDED MODE: IN+ = CH0-CH7, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1, CH2/CH3, CH4/CH5, AND CH6/CH7
Figure 3a. MAX1261 Simplified Input Structure
12-BIT CAPACITIVE DAC REF INPUT CHOLD MUX - + 12pF CH1 CSWITCH CH2 TRACK CH3 T/H SWITCH COM RIN 800 HOLD AT THE SAMPLING INSTANT, THE MUX INPUT SWITCHES FROM THE SELECTED IN+ CHANNEL TO THE SELECTED IN- CHANNEL. COMPARATOR ZERO
The MAX1261/MAX1263 T/H stage enters its tracking mode on the rising edge of WR. In external acquisition mode, the part enters its hold mode on the next rising edge of WR. In internal acquisition mode, the part enters its hold mode on the fourth falling edge of clock after writing the control byte. Note that, in internal clock mode, this occurs approximately 1s after writing the control byte. In single-ended operation, IN- is connected to COM and the converter samples the positive (+) input. In pseudo-differential operation, IN- connects to the negative (-) input, and the difference of (IN+) - (IN-) is sampled. At the beginning of the next conversion, the positive input connects back to IN+ and C HOLD charges to the input signal. The time required for the T/H stage to acquire an input signal depends on how quickly its input capacitance is charged. If the input signal's source impedance is high, the acquisition time lengthens, and more time must be allowed between conversions. The acquisition time, tACQ, is the maximum time the device takes to acquire the signal and is also the minimum time required for the signal to be acquired. Calculate this with the following equation: tACQ = 9(RS + RIN)CIN where RS is the source impedance of the input signal, RIN (800) is the input resistance, and CIN (12pF) is the ADC's input capacitance. Source impedances below 3k have no significant impact on the MAX1261/ MAX1263s' AC performance. Higher source impedances can be used if a 0.01F capacitor is connected to the individual analog inputs. Together with the input impedance, this capacitor forms an RC filter, limiting the ADC's signal bandwidth.
CH0
SINGLE-ENDED MODE: IN+ = CH0-CH3, IN- = COM PSEUDO-DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS CH0/CH1 AND CH2/CH3
Input Bandwidth
The MAX1261/MAX1263 T/H stage offers a 250kHz fulllinear and a 3MHz full-power bandwidth, enabling these parts to use undersampling techniques to digitize high-speed transients and measure periodic signals with bandwidths exceeding the ADC's sampling rate. To avoid high-frequency signals being aliased into the frequency band of interest, anti-alias filtering is recommended.
Figure 3b. MAX1263 Simplified Input Structure
Analog Input Protection
Internal protection diodes, which clamp the analog input to VDD and GND, allow each input channel to swing within (GND - 300mV) to (VDD + 300mV) without damage. However, for accurate conversions near full scale, both inputs must not exceed (VDD + 50mV) or be less than (GND - 50mV). If an off-channel analog input voltage exceeds the supplies by more than 50mV, limit the forward-bias input current to 4mA.
Starting a Conversion
Initiate a conversion by writing a control byte that selects the multiplexer channel and configures the MAX1261/MAX1263 for either unipolar or bipolar operation. A write pulse (WR + CS) can either start an acquisition interval or initiate a combined acquisition plus
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
conversion. The sampling interval occurs at the end of the acquisition interval. The ACQMOD (acquisition mode) bit in the input control byte (Table 1) offers two options for acquiring the signal: an internal and an external acquisition. The conversion period lasts for 13 clock cycles in either the internal or external clock or acquisition mode. Writing a new control byte during a conversion cycle aborts the conversion and starts a new acquisition interval. Internal Acquisition Select internal acquisition by writing the control byte with the ACQMOD bit cleared (ACQMOD = 0). This causes the write pulse to initiate an acquisition interval whose duration is internally timed. Conversion starts when this acquisition interval ends (three external cycles or approximately 1s in internal clock mode) (Figure 4). Note that, when the internal acquisition is combined with the internal clock, the aperture jitter can be as high as 200ps. Internal clock users wishing to achieve the 50ps jitter specification should always use external acquisition mode. External Acquisition Use external acquisition mode for precise control of the sampling aperture and/or dependent control of acquisition and conversion times. The user controls acquisition and start-of-conversion with two separate write pulses. The first pulse, written with ACQMOD = 1, starts an acquisition interval of indeterminate length. The second write pulse, written with ACQMOD = 0, terminates acquisition and starts conversion on WR's rising edge (Figure 5). The address bits for the input multiplexer must have the same values on the first and second write pulse. Power-down mode bits (PD0, PD1) can assume new values on the second write pulse (see the Power-Down Modes section). Changing other bits in the control byte corrupts the conversion.
MAX1261/MAX1263
Reading a Conversion
A standard interrupt signal, INT, is provided to allow the MAX1261/MAX1263 to flag the P when the conversion has ended and a valid result is available. INT goes low when the conversion is complete and the output data is ready (Figures 4 and 5). It returns high on the first read cycle or if a new control byte is written.
Table 1. Control Byte Functional Description
BIT NAME FUNCTION PD1 and PD0 select the various clock and power-down modes. 0 D7, D6 PD1, PD0 0 1 1 D5 ACQMOD 0 1 0 1 Full power-down mode. Clock mode is unaffected. Standby power-down mode. Clock mode is unaffected. Normal operation mode. Internal clock mode selected. Normal operation mode. External clock mode selected.
ACQMOD = 0: Internal acquisition mode ACQMOD = 1: External acquisition mode SGL/DIF = 0: Pseudo-differential analog input mode SGL/DIF = 1: Single-ended analog input mode In single-ended mode, input signals are referred to COM. In pseudo-differential mode, the voltage difference between two channels is measured (Tables 2 and 3). UNI/BIP = 0: Bipolar mode UNI/BIP = 1: Unipolar mode In unipolar mode, an analog input signal from 0 to VREF can be converted; in bipolar mode, the signal can range from -VREF/2 to +VREF/2. Address bits A2, A1, A0 select which of the 8/4 (MAX1261/MAX1263) channels are to be converted (Tables 3 and 4).
D4
SGL/DIF
D3
UNI/BIP
D2, D1, D0
A2, A1, A0
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
tCS CS tCSWS WR tDS D7-D0 CONTROL BYTE ACQMOD = 0 INT tINT1 tDH tWR
tACQ tCSWH
tCONV
RD
HBEN tD0 HIGH-Z DOUT tD01 HIGH/LOW BYTE VALID HIGH/LOW BYTE VALID tTR HIGH-Z
Figure 4. Conversion Timing Using Internal Acquisition Mode
tCS
CS tCSWS WR tDS D7-D0 CONTROL BYTE ACQMOD = 1 tDH CONTROL BYTE ACQMOD = 0 tWR tACQ tCSHW tCONV
tINT1
INT
RD
HBEN tD0 HIGH-Z DOUT tD01 HIGH/LOW BYTE VALID HIGH/LOW BYTE VALID tTR HIGH-Z
Figure 5. Conversion Timing Using External Acquisition Mode 12 ______________________________________________________________________________________
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Selecting Clock Mode
The MAX1261/MAX1263 operate with either an internal or an external clock. Control bits D6 and D7 select either internal or external clock mode. The parts retain the last-requested clock mode if a power-down mode is selected in the current input word. For both internal and external clock mode, internal or external acquisition can be used. At power-up, the MAX1261/MAX1263 enter the default external clock mode. Internal Clock Mode Select internal clock mode to release the P from the burden of running the SAR conversion clock. To select this mode, bit D7 of the control byte must be set to 1 and bit D6 must be set to zero. The internal clock frequency is then selected, resulting in a conversion time of 3.6s. When using the internal clock mode, tie the CLK pin either high or low to prevent the pin from floating. External Clock Mode To select the external clock mode, bits D6 and D7 of the control byte must be set to 1. Figure 6 shows the clock and WR timing relationship for internal (Figure 6a) and external (Figure 6b) acquisition modes with an external clock. For proper operation, a 100kHz to 4.8MHz clock frequency with 30% to 70% duty cycle is recommended. Operating the MAX1261/MAX1263 with clock frequencies lower than 100kHz is not recommended, because it causes a voltage droop across the hold capacitor in the T/H stage that results in degraded performance.
MAX1261/MAX1263
Digital Interface
Input (control byte) and output data are multiplexed on a tri-state parallel interface. This parallel interface (I/O) can easily be interfaced with standard Ps. Signals CS, WR, and RD control the write and read operations. CS represents the chip-select signal, which enables a P to address the MAX1261/MAX1263 as an I/O port. When high, CS disables the CLK, WR, and RD inputs and forces the interface into a high-impedance (high-Z) state. Input Format The control byte is latched into the device on pins D7-D0 during a write command. Table 2 shows the control byte format. Output Format The output format for both the MAX1261/MAX1263 is binary in unipolar mode and two's complement in bipolar mode. When reading the output data, CS and RD must be low. When HBEN = 0, the lower 8 bits are read. With HBEN = 1, the upper 4 bits are available and the output data bits D7-D4 are set either low in unipolar mode or set to the value of the MSB in bipolar mode (Table 5).
ACQUISITION STARTS tCP CLK tCWS tCH WR ACQMOD = 0 tCWH CLK ACQUISITION STARTS tCL
ACQUISITION ENDS
CONVERSION STARTS
WR GOES HIGH WHEN CLK IS HIGH.
ACQUISITION ENDS
CONVERSION STARTS
WR ACQMOD = 0 WR GOES HIGH WHEN CLK IS LOW.
Figure 6a. External Clock and WR Timing (Internal Acquisition Mode)
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
ACQUISITION STARTS ACQUISITION ENDS CONVERSION STARTS
CLK tDH WR ACQMOD = 1 WR GOES HIGH WHEN CLK IS HIGH. ACQMOD = 0 tCWS
ACQUISITION STARTS CLK tDH WR ACQMOD = 1
ACQUISITION ENDS
CONVERSION STARTS
tCWH
WR GOES HIGH WHEN CLK IS LOW.
ACQMOD = 0
Figure 6b. External Clock and WR Timing (External Acquisition Mode)
Table 2. Control Byte Format
D7 (MSB) PD1 D6 PD0 D5 ACQMOD D4 SGL/DIF D3 UNI/BIP D2 A2 D1 A1 D0 (LSB) A0
Table 3. Channel Selection for Single-Ended Operation (SGL/DIF = 1)
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CH0 + + + + + + + + CH1 CH2 CH3 CH4* CH5* CH6* CH7* COM -
*Channels CH4-CH7 apply to MAX1261 only.
14
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Table 4. Channel Selection for Pseudo-Differential Operation (SGL/DIF = 0)
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 CH0 + CH1 + + + + + + + CH2 CH3 CH4* CH5* CH6* CH7*
*Channels CH4-CH7 apply to MAX1261 only.
Applications Information
Power-On Reset
When power is first applied, internal power-on reset circuitry activates the MAX1261/MAX1263 in external clock mode and sets INT high. After the power supplies stabilize, the internal reset time is 10s, and no conversions should be attempted during this phase. When using the internal reference, 500s is required for VREF to stabilize.
Internal and External Reference
The MAX1261/MAX1263 can be used with an internal or external reference voltage. An external reference can be connected directly to REF or REFADJ. An internal buffer is designed to provide +2.5V at REF for both the MAX1261 and the MAX1263. The internally trimmed +1.22V reference is buffered with a +2.05V/V gain.
Internal Reference With the internal reference, the full-scale range is +2.5V with unipolar inputs and 1.25V with bipolar inputs. The internal reference buffer allows for small adjustments (100mV) in the reference voltage (Figure 7). Note that the reference buffer must be compensated with an external capacitor (4.7F min) connected between REF and GND to reduce reference noise and switching spikes from the ADC. To further minimize noise on the reference, connect a 0.01F capacitor between REFADJ and GND. External Reference With both the MAX1261 and MAX1263, an external reference can be placed at either the input (REFADJ) or the output (REF) of the internal reference buffer amplifier. Using the REFADJ input makes buffering the external reference unnecessary. The REFADJ input impedance is typically 17k.
Table 5. Data-Bus Output (8 + 4 Parallel Interface)
PIN D0 D1 D2 D3 D4 D5 D6 D7 HBEN = 0 BIT 0 (LSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIPOLAR (UNI/BIP = 0) BIT 11 BIT 11 BIT 11 BIT 11 HBEN = 1 BIT 8 BIT 9 BIT 10 BIT 11 (MSB) UNIPOLAR (UNI/BIP = 1) 0 0 0 0
50k 50k
+3V
330k
MAX1261 MAX1263 REFADJ
GND
4.7F 0.01F
REF
GND
Figure 7. Reference Voltage Adjustment with External Potentiometer
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
When applying an external reference to REF, disable the internal reference buffer by connecting REFADJ to V DD . The DC input resistance at REF is 25k. Therefore, an external reference at REF must deliver up to 200A DC load current during a conversion and have an output impedance less than 10. If the reference has higher output impedance or is noisy, bypass it close to the REF pin with a 4.7F capacitor. rising edge on WR causes the MAX1261/MAX1263 to exit shutdown mode and return to normal operation. To achieve full 12-bit accuracy with a 4.7F reference bypass capacitor, 500s is required after power-up. Waiting 500s in standby mode, instead of in full-power mode, can reduce power consumption by a factor of 3 or more. When using an external reference, only 50s is required after power-up. Enter standby mode by performing a dummy conversion with the control byte specifying standby mode. Note: Bypassing capacitors larger than 4.7F between REF and GND results in longer power-up delays.
Power-Down Modes
Save power by placing the converter in a low-current shutdown state between conversions. Select standby mode or shutdown mode using bits D6 and D7 of the control byte (Tables 1 and 2). In both software powerdown modes, the parallel interface remains active, but the ADC does not convert. Standby Mode While in standby mode, the supply current is 850A (typ). The part powers up on the next rising edge on WR and is ready to perform conversions. This quick turn-on time allows the user to realize significantly reduced power consumption for conversion rates below 250ksps. Shutdown Mode Shutdown mode turns off all chip functions that draw quiescent current, reducing the typical supply current to 2A immediately after the current conversion is completed. A
Transfer Function
Table 6 shows the full-scale voltage ranges for unipolar and bipolar modes. Figure 8 depicts the nominal, unipolar input/output (I/O) transfer function and Figure 9 shows the bipolar I/O transfer function. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = (VREF / 4096).
Maximum Sampling Rate/ Achieving 300ksps
When running at the maximum clock frequency of 4.8MHz, the specified throughput of 250ksps is achieved by completing a conversion every 19 clock cycles: 1 write cycle, 3 acquisition cycles, 13 conver-
OUTPUT CODE
FULL-SCALE TRANSITION
OUTPUT CODE FS = REF + COM 2 ZS = COM -FS = -REF + COM 2 REF 4096
111 . . . 111 111 . . . 110
FS = REF + COM ZS = COM REF 1 LSB = 4096
011 . . . 111 011 . . . 110
100 . . . 010 100 . . . 001 100 . . . 000 011 . . . 111 011 . . . 110 011 . . . 101
000 . . . 010 000 . . . 001 000 . . . 000 111 . . . 111 111 . . . 110 111 . . . 101
1 LSB =
000 . . . 001 000 . . . 000 0 1 2 2048 INPUT VOLTAGE (LSB) FS 3/2 LSB
100 . . . 001 100 . . . 000 FS *COM VREF / 2 - FS COM* INPUT VOLTAGE (LSB) +FS - 1 LSB
(COM)
Figure 8. Unipolar Transfer Function 16
Figure 9. Bipolar Transfer Function
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Table 6. Full Scale and Zero Scale for Unipolar and Bipolar Operation
UNIPOLAR MODE Full scale Zero scale -- VREF + COM COM -- Zero scale Negative full scale BIPOLAR MODE Positive full scale VREF/2 + COM COM -VREF/2 + COM
sion cycles, and 2 read cycles. This assumes that the results of the last conversion are read before the next control byte is written. Throughputs up to 300ksps can be achieved by first writing a control word to begin the acquisition cycle of the next conversion, then reading the results of the previous conversion from the bus (Figure 10). This technique allows a conversion to be completed every 16 clock cycles. Note that the switching of the data bus during acquisition or conversion can cause additional supply noise, which can make it difficult to achieve true 12-bit performance.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1261/MAX1263 are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Layout, Grounding, and Bypassing
For best performance, use printed circuit (PC) boards. Wire-wrap configurations are not recommended since the layout should ensure proper separation of analog and digital traces. Do not run analog and digital lines parallel to each other, and do not lay out digital signal paths underneath the ADC package. Use separate analog and digital PC board ground sections with only one star point (Figure 11) connecting the two ground systems (analog and digital). For lowest noise operation, ensure the ground return to the star ground's power supply is low impedance and as short as possible. Route digital signals far away from sensitive analog and reference inputs. High-frequency noise in the power supply (VDD) could influence the proper operation of the ADC's fast comparator. Bypass VDD to the star ground with a network of two parallel capacitors, 0.1F and 4.7F, located as close as possible to the MAX1261/MAX1263s' powersupply pin. Minimize capacitor lead length for best supply-noise rejection; add an attenuation resistor (5) if the power supply is extremely noisy.
Aperture Definitions
Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture delay (tAD) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. Therefore, SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency's RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 x log (SignalRMS / NoiseRMS)
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
WR RD
HBEN CONTROL BYTE D7-D0 D11-D8 LOW BYTE STATE HIGH BYTE CONVERSION CONTROL BYTE D7-D0 LOW BYTE D11-D8 HIGH BYTE
D7-D0
ACQUISITION
ACQUISITION
SAMPLING INSTANT
Figure 10. Timing Diagram for Fastest Conversion
Effective Number of Bits
Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76) / 6.02
SUPPLIES +3V VLOGIC = +2V/+3V GND
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
R* = 5
4.7F 0.1F
VDD
GND
COM
+2V/+3V DGND DIGITAL CIRCUITRY
THD = 20 x log V22 + V32 + V4 2 + V52 / V1 where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
*OPTIONAL
MAX1261 MAX1263
Figure 11. Power-Supply and Grounding Connections
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion component.
Chip Information
TRANSISTOR COUNT: 5781 SUBSTRATE CONNECTED TO GND
18
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250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface
Typical Operating Circuits
CLK VLOGIC +1.8V TO +3.6V +3V +2.5V 0.1F 4.7F P CONTROL INPUTS CS WR RD HBEN INT CH7 D7 D6 D5 D4 D3/D11 D2/D10 D1/D9 D0/D8 CH6 CH5 CH4 CH3 CH2 CH1 CH0 COM GND ANALOG INPUTS D7 D6 D5 D4 D3/D11 D2/D10 D1/D9 D0/D8 CH3 CH2 CH1 CH0 COM GND ANALOG INPUTS OUTPUT STATUS INT OUTPUT STATUS CLK VLOGIC +1.8V TO +3.6V +3V +2.5V 0.1F 4.7F
MAX1261/MAX1263
MAX1261 VDD
P CONTROL INPUTS CS WR RD HBEN REF REFADJ
MAX1263 VDD
REF REFADJ
P DATA BUS
P DATA BUS
Pin Configurations (continued)
TOP VIEW
HBEN 1 D7 2 D6 3 D5 4 D4 5 D3/D11 6 D2/D10 7 D1/D9 8 D0/D8 9 INT 10 RD 11 WR 12 24 VLOGIC 23 VDD 22 REF 21 REFADJ 20 GND
Ordering Information (continued)
PART MAX1263ACEG * MAX1263BCEG * TEMP RANGE 0C to +70C 0C to +70C PIN-PACKAGE 24 QSOP 24 QSOP 24 QSOP 24 QSOP INL (LSB) 0.5 1 0.5 1
MAX1263AEEG * -40C to +85C MAX1263BEEG* -40C to +85C
* Future product--contact factory for availability.
MAX1263
19 COM 18 CH0 17 CH1 16 CH2 15 CH3 14 CS 13 CLK
QSOP ______________________________________________________________________________________ 19
250ksps, +3V, 8-/4-Channel, 12-Bit ADCs with +2.5V Reference and Parallel Interface MAX1261/MAX1263
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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